The LEDLUM project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement No. 731466.
Results of 1st period
The majority of solid state light (SSL) systems is using light emitting diodes (LED) as the light source. The whole lighting system consists of the electrical part (light engine), the mechanical part (luminaire) and the optical part (reflector and lens). The bottleneck for size, weight and cost reduction as well as reliability and energy efficiency increase is the light engine, therefore LEDLUM focuses on this part.
The light engine contains an LED module and a driver. The LED is responsible for the limit in energy efficacy (lm/W), but the driver is limiting factor for size, weight, cost and reliability. To operate the LEDs from the electric grid, the driver needs to convert electrical energy from the grid to voltage and current levels, that applies to the LEDs electrical characteristics. LEDLUM is committed to make a major innovation step in overall solid-state lighting engines by
- 90% size and weight reduction of the power electronics part in the LED driver,
- reducing material cost by a factor of 2,
- reducing energy losses by 45 %;
- increasing the expected lifetime from 5 to 10 years.
The major novel concepts developed are:
- increasing switching frequency of grid-interfaced power electronics by a factor of 1000 (to 50 to 100 MHz) with state-of-the-art System in Package (SIP) integration
- which enables usage of magnetics inductors (up to 360 nH/mm2) and ultra-high-density capacitors (up to 500 nF/mm2) on silicon
- innovative unprecedented circuit design.
The methods therefore include integrated magnetics, deep-trench silicon level capacitor design, integrated circuit level power electronics and mechanical design for optics and end customer ready demonstrators.
In WP1 the first complete description of the system architecture came in place in time for D1.2 (“SAnR v1.0”) and D1.3 (“SAnR v6.0”). This required several iterations between the consortium partners, and makes a very solid foundation for the project incl. both system requirements and architecture as well as requirements and specifications for each of the sub blocks. It is the basis for the work carried out on passives (WP2), semiconductors (WP3), power electronics (WP4) and driver system (WP5).
Within WP2 a state of the art review for sputtered soft magnetic materials has identified CZTB as a promising first candidate material which shows a significant improvement over the present plated material. Consequently, CZTB is the choice of material for fabricating the generation 1 magnetic devices. Laminated films of CZTB and dielectric material have been fabricated and characterised in relation to their magnetic properties. The development of a patterning process for laminated CZTB stacks has been completed. Furthermore a dummy run to fabricate strip-line device using the CZTB process flow has also been completed. The final magnetic devices for the first System-in-Package (SiP) is in production and will be ready for use within the coming month.
Process selection for full integration narrowed down to 3 options in WP3: AMS, X-FAB and ST. Discrete (e.g. naked dies) GaN FETs are identified as a potential other solution. Furthermore, integrated custom designed GaN FETs from Fraunhofer are under investigation.
A start-up circuit for the Class-E inverters from WP4 was designed, simulated, laid out and sent for production as a tape-out in the AMS 180nm, 50 V process. The start-up circuitry contains a sensing stage, non-overlapping clock generator for creating the dead time and a tri-transistor output stage, that can interface to the discrete self-oscillating gate drive circuitry as implemented in the first mock-up of WP4.
In WP4 the design and implementation of mock-up as preparation work for the first prototype of the AC/DC is ongoing with fruitful collaboration with WP2. The chosen topology is based on a resonant inverter, a common Class-DE rectifier. The passive components used herein are mainly constructed discretely. On the DC/DC side both a low and high voltage design have been develop, both to give input for the interface discussions between the AC/DC and the DC/DC and as preparation for the first prototype.
The interface between the AC/DC and DC/DC have been examined thoroughly and the tradeoffs between various nominal voltages and the allowed low frequency ripple have been discussed. Based on this, an AC/DC and DC/DC module have been developed and is now ready for system integration in WP5.
Investigation of various PWM modulation techniques have been carried out in WP5 both with an open and closed loop DC/DC converter prototype. One of them proved to simultaneously fulfil the dimming requirements and the flicker requirements according to IEEE 1789.
A first prototype of the low-voltage power supply (LVPS) was build, tested and used in the low voltage DC/DC converter.
Currently system integration is performed in order to build a complete LED driver consisting of the AC/DC, DC/DC, LVPS and the control and DALI interface. This system is expected to be ready for delivery to WP6 at the end of July.